proc defaultSimOutputKeepList {streamName} {

    output keepList  $streamName -add BMUD_StorableBank
    output keepList  $streamName -add BSUD_StorableBank
    output keepList  $streamName -add CEMD_StorableBank
    output keepList  $streamName -add CESD_StorableBank
    output keepList  $streamName -add CHAD_StorableBank
    output keepList  $streamName -add CMPD_StorableBank
    output keepList  $streamName -add CMUD_StorableBank
    output keepList  $streamName -add CMXD_StorableBank
    output keepList  $streamName -add COTM_StorableObject
    output keepList  $streamName -add COTQ
    output keepList  $streamName -add CPRD_StorableBank
    output keepList  $streamName -add CSPD_StorableBank
    output keepList  $streamName -add CSXD_StorableBank
    output keepList  $streamName -add DBUsedSetInfoList
    output keepList  $streamName -add ErrorSummary
    output keepList  $streamName -add EVCL_StorableBank
    output keepList  $streamName -add HEPG_StorableBank
    output keepList  $streamName -add HEP4_StorableBank
    output keepList  $streamName -add ISLD_StorableBank
    output keepList  $streamName -add LRIH_StorableBank
    output keepList  $streamName -add MISL_StorableBank
    output keepList  $streamName -add MSVX_StorableBank
    output keepList  $streamName -add OBSP_StorableBank
    output keepList  $streamName -add OBSV_StorableBank
    output keepList  $streamName -add PEMD_StorableBank
    output keepList  $streamName -add PESD_StorableBank
    output keepList  $streamName -add PHAD_StorableBank
    output keepList  $streamName -add PPRD_StorableBank
    output keepList  $streamName -add ReleaseHistory
    output keepList  $streamName -add SIXD_StorableBank
    output keepList  $streamName -add TOFD_StorableBank
    output keepList  $streamName -add TSUD_StorableBank
    output keepList  $streamName -add WHAD_StorableBank
    output keepList  $streamName -add MVTX_StorableBank
    output keepList  $streamName -add PropagatedSiParticleColl   
    output keepList  $streamName -add HitOBSPNumberColl       
}

# This sets up the output file including which banks to write
if {![info exists output_setup] || ![string match 'yes' '$output_setup']} {
if {![info exists sim_outfile]} {set sim_outfile ./${process_name}.sim}
module output FileOutput
talk FileOutput
  output create main_stream $sim_outfile
  output path main_stream AllPath

  # Add simulation objects to keepList:
  defaultSimOutputKeepList main_stream

  # droplist:
  output dropList main_stream CT_HitSet PhysicsTowerData
  output dropList main_stream -add CdfTrackHits:"COT Hits for CdfTrack"
  output dropList main_stream -add StorableRun2SiStripSet:""

  # Additional objects in keeplist:
  output keepList main_stream -add TC1D_StorableBank 
  output keepList main_stream -add TC2D_StorableBank
  output keepList main_stream -add TL2D_StorableBank
  output keepList main_stream -add CdfTrackMatch
  output keepList main_stream -add SIXD_StorableBank
  output keepList main_stream -add SIXD_StorableBank:"Corrected"

  main_stream
    compression set t
  exit
  output list

exit
}