" vme fifo module 94/12/19


module  FIFO1
title   'VME FIFO MODULE PROTOCOL'
FIFO01  device  'P16V8S';

No,Yes,X = 1,0,.X.;  "Negative logic

        " INPUT

AM0,AM1,AM2     pin     3,4,5;
AM3,AM4,AM5     pin     6,7,8;
        AM  = [AM5,AM4,AM3,AM2,AM1,AM0];
        AMHIGH = [AM5,AM4];
        A32 = (AMHIGH == 0);
	A24 = (AMHIGH == 3);
	A16 = (AMHIGH == 2);

_LWORD          pin     2;
_IACK           pin     9;
_WRITE          pin     11;
A1		pin	12;
	LWADR = !A1;

_ADR1,_ADR2,_ADR3  pin     1,19,18;
        ADR    = !_ADR1 & !_ADR2 & !_ADR3;
        ADR24  = !_ADR1 & !_ADR2;
        ADRSEL = ( A24 & ADR24 # A32 & ADR ) & _IACK;
        ADRPIN = [_ADR1,_ADR2,_ADR3];

_RSTPAT         pin     14;

        " OUTPUT

_IR,_W,_R       pin     17,16,15;       " IR .. INNER RESET
_R16		pin	13;

        equations

!_W   = ADRSEL & !_WRITE;
!_R   = LWADR & ADRSEL & _WRITE;
!_R16 = !LWADR & ADRSEL & _WRITE & _LWORD;
!_IR  = ADRSEL & !_WRITE & ( !_RSTPAT # _LWORD );

        test_vectors 
([AM,ADRPIN,A1,_LWORD,_IACK,_WRITE,_RSTPAT] -> [_R,_W,_IR])
 [^h09,0   ,0 ,  Yes ,  No ,  No  ,   X   ] -> [Yes,No,No];
 [^h09,0   ,0 ,  Yes ,  No ,  Yes ,  No   ] -> [No,Yes,No];
 [^h09,0   ,0 ,  Yes ,  No ,  Yes ,  Yes  ] -> [No,Yes,Yes];
 [^h09,1   ,0 ,  Yes ,  No ,  Yes ,  Yes  ] -> [No,No,No];

end





module  FIFO2
title   'VME FIFO MODULE PROTOCOL'
FIFO02  device  'P16V8R';

Z,X,C,L,H       = .Z., .X., .C., 0, 1;
CLK,_OE          pin     1,11;

        " INPUT

_W,_R           pin     2,3;
_DS0,_DS1       pin     4,5;
        DTSTRB = !_DS0 & !_DS1;

_EF1,_EF2       pin     6,7;
        EMPTYSTATE = !_EF1 # !_EF2;

HF		pin     8;
_R16		pin	9;

        " OUTPUT

_RSTS		pin	19;
_RFIFO          pin     17;
_RSEL           pin     16;
_MSEL           pin     15;
_HALF           pin     14;
_EMPTY          pin     13;
DS              pin     12;

        equations

DS      = DTSTRB;                   " use for clk

!_HALF  := HF;
!_EMPTY := EMPTYSTATE;
!_MSEL  := !_W # !_R # !_R16;	" module select
!_RFIFO := !_R & !EMPTYSTATE;	" can read data from fifo
!_RSEL  := !_R;			" to make gate for 3state buffer
!_RSTS  := !_R16;		" read status

        test_vectors 
([ _DS0,_DS1] ->  DS )
 [   L , H  ] ->  L ;
 [   L , L  ] ->  H ;

        test_vectors
([ CLK,_W,_R,_EF1,_EF2] -> [_EMPTY,_MSEL,_RFIFO,_RSEL] )
 [  C , H, L,  L ,  L ] -> [   L  ,  L  ,   H  ,  L  ];
 [  C , H, L,  H ,  H ] -> [   H  ,  L  ,   L  ,  L  ];
 [  C , L, H,  H ,  H ] -> [   H  ,  L  ,   H  ,  H  ];
         
end





module  FIFO3
title   'VME FIFO MODULE PROTOCOL'
FIFO03  device  'P16V8C';

Z,X,C,L,H       = .Z., .X., .C., 0, 1;

        " INPUT

POWERON         pin     1;
_IR,_SRST       pin     2,3;    " SRST .. SYSRESET
_FRONTRESET     pin     15;

_FF1,_FF2       pin     8,9;
        FULLSTATE = !_FF1 # !_FF2;

DLYDS2          pin     4;
_RFIFO          pin     5;
_RSEL           pin     6;
_MSEL           pin     7;
DS              pin     11;
	RESETSIGNAL = !_FRONTRESET # POWERON # ( !_IR & DS ) # !_SRST;
	DSWINDOW = DS & DLYDS2;

_RSTS		pin	18;

        " OUTPUT

FULL,_RESET     pin     14,13;
_GATE           pin     16;
DTACK           pin     19;
_DSR            pin     12;             " use fifo read
_G16		pin	17;

        equations

!_DSR   = !_RFIFO & DSWINDOW;
FULL    = FULLSTATE;
!_RESET = RESETSIGNAL;
DTACK   = !_MSEL & DSWINDOW;
!_GATE  = (!_RSEL # !_RSTS ) & DSWINDOW;
!_G16   = !_RSTS & DSWINDOW;

        test_vectors
([_MSEL,DLYDS2, DS] -> DTACK)
 [  H  ,  L   , H ] ->   L ;
 [  L  ,  L   , H ] ->   L ;
 [  L  ,  L   , H ] ->   L ;
 [  L  ,  H   , H ] ->   H ;

        test_vectors
([_RFIFO,_RSEL,DLYDS2, DS] -> [_DSR,_GATE])
 [  L   ,  L  , L    , H ] -> [  H ,  H  ];
 [  L   ,  L  , H    , H ] -> [  L ,  L  ];
 [  H   ,  L  , H    , H ] -> [  H ,  L  ];

end